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  • ASIC Design/Verification:  KarMic offers design verification services for Analog/RF, Digital and Mixed signal ICs. Its verification team is highly appreciated by customers for dedication, commitment and quality which has enabled several successful first pass silicon results. Working closely with customer's design team, KarMic has built trust and support. It is greatly appreciated by the designers for professional work. The verification team handles projects that involve:
    • Modeling and simulation of entire chip functionality using HDL.
    • Top level verification by co-simulation.
    • Spec validation.
    • Module-level verification of Analog/RF design.
    • RTL verification.

    The team also supports in post-silicon debug by assisting in the test environment setup re-using pre-silicon test case information.

  • Analog & Mixed Signal Design:  KarMic has its Analog, Digital (Mixed Signal) Layout Design and Circuit design teams working closely with various teams in Texas Instruments - Bangalore, Dallas, and Nice.

    The analog layout engineers are involved in the layout design for power management, USB, wireless modules of the chip including low drop out regulators, DCDC converters, reference generators, battery chargers, charge pumps, drivers, data converters, PLLs, DLL, transmitters, receivers, LNAs, mixers, filters. The vivacious group has expertise in handling mixed signal chips on 400nm, 130nm, 90n m, 60nm, 40nm, 28nm technology nodes.

    The team also has experience in handling the full chip mixed signal activity with aggressive schedules. The dynamic analog layout team has developed unique ways of floor planning, matching of devices, routing, critical shielding and power planning that has led to the success of various chips.

    With constant reviews from customers and internally, the releases are back-annotated to meet or improve the specification manuals. The smart cosy digital team is involved in floor planning, PnR, CTS, timing optimization and power analysis, signal integrity analysis that leads to brilliant execution of RTL to GDSII Hierarchical flow.

    Advantage of Mixed Signal KarMic:
    • Expertise in all tech nodes and experience in handling aggressive schedules.
    • Enthusiastic group that trains and shares knowledge.
    • Self-driven scripting team that develops scripts to ease the layout activity.
    • Leaders who continuously involve in successful release of full chips.
    • In depth knowledge of the VLSI process and flow for phenomenal execution.

Embedded Design Services:

  • Core expertise in:
    • Firmware development in ARM Cortex - MO, M3, M4, M7, A5, A7, A15
    • FreeRTOS
    • Linux Device Drivers, bootloader development
    • Hardware Development including design and validation
    • Designed board up to 1 2 layers
    • Mechanical design (Industry Design & Machine Design)
    • Idea - Production - EOL
  • Services Offered:
    • Driver Development and Validation
    • Embedded Development, Validation and Maintenance
    • BSP Porting and Validation
    • Board Design, bring up and Diagnostics
    • Staffing Augmentation services
    • Inhouse Complete product development


  • Analog Layout Skills and Expertise:  The KarMic team has a wide range of over 18 years of experience handling custom layout modules. With skills in effort estimation, area estimation, floor planning, power planning, signal planning, module development, pad frame development, full chip integration, technology migration, area optimization, and design shrink, the KarMic team has handled technologies that include: 5nm, 7nm, 14nm, 20nm, 28nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm, 380nm.
  • AMS Layout Training:  KarMic has tie-up with MIT to use Cadence tool in their labs for the layout design and characterization of the cells.

    Imparting 6+ months of layout training on various blocks like inverter, level shifter array, and amplifier upto LDO (400 MA) module; along with, programming language skill for small scripts. Key concepts include: floor plan, power plan, time estimation, substrate isolation, matching, shielding, critical signal routing, EM etc.

  • RF Layout:  KarMic has handled RF layouts with frequencies ranging from 10 GHz to 160 GHz, major test chip / IP’s.

    The module support includes: Complete ownership of all the blocks/modules, area estimation, floor planning with hierarchical full chip approach, and layout from scratch to final hand-over after verification checks.

    The major sub-modules handled include: Transmitter (FILTERS, MIXER, LO, PLL, PA); Receivers (FILTERS, LNA, MIXER, LO, PLL); Baseband (ADC, DAC, COMPARATORS, BIAS circuits); the transmission lines (TL) and Transformer (XFMR); Clock Distribution, Baseband amplifier, PFD & BIAS, Filters; Hall sensors, hard disk read write drivers; and GM filters, Power Amplifiers, Up converters etc.

    The full-chip support includes test-chip support with flexibility to work effectively with extended hours with world-wide customers.

    Further to the above, KarMic offers SOC integration support.

  • Verification:  KarMic has over 14+ years of experience in the top-level mixed signal SOC verification. Have helped customer specific mixed signal SOC verification flow development which is being extensively used for verification and has resulted in highly functional first pass silicon.

    KarMic Team works on full chip verification which involves RTL/Gate-level verification of digital and schematic verification of Analog modules in a top level mixed-signal environment.

    We develop functional models for Analog blocks using VHDL RN, wreal or vams modeling concepts.

    We study the specifications and come up with a simulation plan for both RTL verification as well as Analog module verification from top-level perspective.

    We set up test-bench and build test cases to verify the scenarios mentioned in simulation plan using SV and UVM concepts. Report any bugs found in design to Digital design/Analog design/ System design teams.
    In addition to reporting bugs, the team also debugs RTL issues, hook-up issues and schematic issues and report the root cause for bugs to design team.

    We track all the bug fixes, and follow-up with design team until there is closure on all the bugs and the fixes are verified again.

    Apart from the above; we execute CODE coverage to ensure good RTL coverage in top level simulations. We run Gate level simulations with SDFs included and look for any timing violations. We effectively track the simulation plan coverage, report status and review results with customer to ensure good quality first pass silicon. We also deliver procedures to TEST team for post-silicon validation.

  • AMS Verification Training:  We have tie-up with MIT to use Cadence tool at their labs for layout, simulations and AMS verification. The training includes:
    • Verilog training: Includes modeling and verifying combinational, complex combinational, sequential logics, memories, interface protocols like I2C.
    • Verilog AMS Training: Includes modeling wreal and electrical models for a few Analog blocks like LDO, BUCK, PLL and ADC. Started with a mini project of verifying a PMIC which includes understanding the Spec, block diagram, timing diagram and building wreal and electrical models. This also includes TOP level hook-up and verifying from TOP level.
    • SV and UVM Training: Includes learning basics of SV-UVM concepts, understanding different components like driver, monitor, sequencer and scoreboard. They will build SV-UVM environment around the same PMIC which they implemented above.
  • System and Software Capability:  This includes:
    • Firmware development around micro controllers such as ARM/MSP430/C2000.
    • Migrating application between processors and boards.
    • Customer support for application development.
    • Productizing EVM boards.
    • Firmware code / Library management.
  • New Domains:  Medical Electronics, Solar Energy, and LED Efficiency.
  • New Applications:  Smart Devices, Sensors & Communications; MEMS & Wearable Computing; and Internet of Things (IOT).